An Interactive System Level Simulation Environment for Systems on Chip

This article presents an interactive simulation environment for high level models intended for Design Space Exploration of Systems-On-Chip. Our coarse grained sim- ulation methodology which allows for efficient system level performance estimations was detailed in the scope of our last year's submission (4). Our new achievement comprises an additional module which allows the designer to control the simulation in real time by performing step wise execution, saving and restoring simulation states as well as providing live feedback to a graphical interface. Finally, this article gives an idea of possible enhancements of the simulation environment in order to automatically assess several possible executions of tasks and thus enhance simulation coverage. I. INTRODUCTION The increasing complexity of today's embedded systems requires an evaluation of benchmark data as early as possible in the design flow. At early design stages, low level models of the Systems-On-Chip are not available yet. Design Space Exploration aims at identifying the most suitable hardware / software platform complying to given constraints. This stage is accomplished based on high level models of the target system, on which fast simulations and static formal analysis can be performed in order to verify the satisfiability of both functional and non functional requirements. In this context, we have previously introduced a UML-based environment, named DIPLODOCUS ((3), (5)). The strength of our approach relies on formal verification capabilities, and fast simulation techniques. DIPLODOCUS design approach is based on the following fundamental principles: • Use of a high level language (UML). • Clear separation between application and architectural matters. • Data abstraction. • Use of fast simulation and static formal analysis tech- niques, both at application and mapping levels. Moreover, DIPLODOCUS includes the following 3-step methodology: