Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber
2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC)(2021)
摘要
Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.
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关键词
operand polynomials,optimized polynomial multiplier architectures,post-quantum KEM Saber,ongoing NIST post-quantum cryptography standardization project,Saber's computation time,polynomial multiplications,polynomial rings,powers-of-two moduli,optimization strategies,different hardware platforms,diverse application goals,high-speed architectures
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