Implementing the scale vector-thread processor
ACM Trans. Design Autom. Electr. Syst.（2008）
摘要
The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache. An automated and iterative design and verification flow enabled a performance-, power-, and area-efficient implementation with two person-years of development effort. Scale has a core area of 16.6 mm2 in 180 nm technology, and it consumes 400 mW--1.1 W while running at 260 MHz.
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关键词
vector processors,development effort,iterative vlsi design flow,hybrid c++/verilog simulation,core area,embedded computing,procedural datapath pre-placement,iterative design,multithreaded processors,scale vector-thread processor,decoupled execution cluster,complexity-effective solution,area-efficient implementation,vector load,multithreaded processing,vector-thread processors,vlsi design,vector processor,chip
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