RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2008)
摘要
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical to success. We present a new physical synthesis optimization for latch placement called RUMBLE (Rip Up and Move Boxes with Linear Evaluation) that uses a linear timing model to optimize timing by simultaneously re-placing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effectiveness of the approach: our techniques improve slack by 41.3% of cycle time on average for a large commercial ASIC design
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关键词
linear timing model,physical synthesis tool,incremental timing-driven physical-synthesis optimization,timing-driven placement,critical path,timing closure,130-nm design,multiple cycle,physical-synthesis optimization algorithm,new physical synthesis optimization,multiple gate,physical-synthesis tool,cycle time,linear evaluation,static timing analysis
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