An Eda-Friendly Protection Scheme Against Side-Channel Attacks
DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe(2013)
摘要
This paper introduces a generic and automated methodology to protect hardware designs from side-channel attacks in a manner that is fully compatible with commercial standard cell design flows. The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical device more difficult to attack. Timing constraints are then specified to commercial EDA tools, which restore the circuit functionality and efficiency while preserving the introduced randomness. The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows.
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关键词
AES-128 hardware implementation,FPGA design flow,commercial EDA tool,commercial standard cell design,hardware design,signal timing,timing constraint,automated methodology,circuit functionality,cryptographic unit,EDA-friendly protection scheme,side-channel attack
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