Simultaneous optimization of driving buffer and routing switch sizes in an FPGA using an iso-area approach
ISVLSI(2002)
摘要
In this paper, we analyze the gain from simultaneous sizing of driving buffers and routing switches on an FPGA interconnect performance. We show that it is not area feasible to build FPGAs with optimally sized interconnects. However, with constrained interconnect area, it is possible to significantly improve the speed of interconnects by simultaneously sizing the driving buffers and routing switches. Our experiments suggest that by simultaneously optimizing the routing resources, delay can be improved by 15-20%. We introduce the idea of iso-area optimization in which we find optimal sizing of routing resources within an overall area constraint. We also show that by making the routing architecture heterogeneous, in terms of routing switch size, we can further improve the performance of an FPGA by 1-12%
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关键词
heterogeneous routing architecture,integrated circuit interconnections,delay improvement,network routing,routing resource,iso-area optimization,switch size,fpga interconnect performance,routing architecture,routing resources optimization,circuit optimisation,delays,optimal sizing,routing switch size optimization,driving buffer,overall area constraint,critical path analysis,fpga,buffer circuits,routing switch sizes,constrained interconnect area,iso-area approach,simultaneous optimization,integrated circuit layout,critical path delay,field programmable gate arrays,simultaneous sizing,driving buffer optimization,very large scale integration,constraint optimization,routing,switches
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