A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Amit Agarwal,Sanu Mathew,Steven Hsu,Mark Anders,Himanshu Kaul,Farhana Sheikh,Rajaraman Ramanarayanan,Suresh Srinivasan,Ram Krishnamurthy,Shekhar Borkar

ISSCC（2010）

引用 48|浏览64

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摘要

A 32 nm on-die fine-grained reconfigurable fabric for DSP/media accelerators is fabricated and occupies a 0.076 mm2 die. The optimized hybrid arithmetic configurable logic blocks with self-decoded look-up tables, ultra-low voltage PVT-tolerant register file circuits and dual-supply operation help enable a 2.4 GHz nominal performance at 1.0 V and 320 mV-to-1.2 V dynamic voltage range. The peak energy efficiency is 2.6TOPS/W when measured at 340 mV and 50Â°C.

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关键词

cmos integrated circuits,hybrid arithmetic configurable logic blocks,ultra-low voltage pvt-tolerant register file circuits,dsp,media accelerators,reconfigurable architectures,uhf integrated circuits,digital signal processing chips,frequency 2.4 ghz,voltage 320 mv to 1.2 v,size 32 nm,logic design,self-decoded look-up tables,on-die fine-grained reconfigurable fabric,cmos,table lookup,temperature 50 c,look up table,adders,register file,energy efficient,registers

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