Linewidth reduction using liquid ashing for sub-100 nm critical dimensions with 248 nm lithography

The need for sub-100 nm semiconductor devices has driven our industry to develop new resists, exposure tools (248 nm, 193 nm, extreme ultraviolet, SCALPEL, etc.), mask technologies, and processing procedures. An enormous amount of research has gone into every aspect of the semiconductor device fabrication process and new techniques to further reduce the critical dimensions need to be investigated. The work that is reported on in this article identifies a process that is referred to as liquid ashing. Liquid ashing is a novel approach to linewidth reduction of resist features patterned with positive 248 nm deep-ultraviolet (DUV) resists. The lashing process reduces linewidth through the use of a second wet development step. This process is isotropic and can be continued once started. A bake prior to the second development improves process control. Various types of phase-shifted patterns have been measured and evaluated to determine the effectiveness of this process. This process has been exercised using different resists, different developers, and several different integrated circuit (IC) test patterns. Linewidth reduction using liquid ashing is controllable, does not increase linewidth variations, and can be accomplished using existing equipment. The process was evaluated with IC test patterns that were printed using attenuated phase shifted mask technology generated photo masks and conventional DUV processes. Scanning electron microscopy was used to obtain critical dimension data and cross-sectional information. Features, ranging from 120 to 280 nm in size were reduced by 60 nm at a controllable rate of approximately 1.25 nm/s. Transistor gates as small as 60 nm have been formed in 248 nm DUV resist and successfully transferred while maintaining >85degrees wall profile. (C) 2001 American Vacuum Society.