mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement

The rapid advance of VLSI technology has created an increasing demand for highquality placement tools. A placer has to deliver solutions that meet all the design requirements in a rapid fashion without wasting any computational resources. The nanometer technology makes it possible to integrate billions of transistors in a single chip. Such a design complexity, combined with the increasingly stringent market pressure, requires a very efficient implementation of the placement algorithms. A modern design scenario usually involves several iterations between the logic synthesis and physical design before timing closure can be achieved. From a design iteration point of view, an efficient placement algorithm is essential. Moreover, shrinking feature sizes introduce a full spectrum of deep submicron effects, such as interconnect dominance, crosstalk, IR drop, etc., which challenge the chip designers more than ever before. A placer needs to address explicitly timing, congestion, signal integrity, etc., so that the design can be signed off in a timely manner to meet the shrinking market window.