A 15-Bit Binary-Weighted Current-Steering Dac With Ordered Element Matching

Device variability has become one of the fundamental challenges to high-resolution and high-accuracy DACs in nanometer and emerging processes. This paper introduces a 15-bit binary-weighted current-steering DAC in a standard 130nm CMOS technology, which utilizes a new random mismatch compensation theory called ordered element matching to improve the static linearity performance with the presence of large variability. The chip's core area is less than 0.42mm(2), among which the 7-bit MSB current source area is well within 0.021mm(2). Measurement results have shown that the DAC's DNL and INL can be reduced from 9.85LSB and 17.41LSB to 0.34LSB and 0.77LSB, respectively.