Robust partitioning for hardware-accelerated functional verification

Design Automation Conference, 2011, Pages 854-859.

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classical hypergraphcut directionalityinstruction memorymillion gatemassively-parallel hardwareMore(22+)

Abstract:

We introduce a method of partitioning for massively-parallel hardware accelerated functional verification. Our approach augments classical hypergraph partitioning to model temporal dependencies that maximize parallelization within the instruction memories of the machine. Simulation depth is further reduced by optimizing path criticality a...More

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