Increasing The Size Of Atomic Instruction Blocks Using Control Flow Assertions

Sj Patel, T Tung, S Bose, Mm Crum

MICRO(2000)

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摘要
For a variety of reasons, branch-less regions of instructions are desirable for high-performance execution. In this paper, we propose a means for increasing the dynamic length of branch-less regions of instructions for the purposes of dynamic program optimization. We call these atomic regions frames and we construct them by replacing original branch instructions with assertions. Assertion instructions check if the original branching conditions still hold. If they hold, no action is taken. If they do not, then the entire region is undone. In this manner, an assertion has no explicit control flow. We demonstrate that using branch correlation to decide when a branch should be converted into an assertion results in atomic regions that average over 100 instructions in length, with a probability of completion of 97%, and that constitute over 80% of the dynamic instruction stream. We demonstrate both static and dynamic means for constructing frames. When frames are built dynamically using finite sized hardware, they average 80 instructions in length and have good caching properties.
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关键词
cache storage,computer architecture,performance evaluation,atomic instruction blocks,branch instructions,caching properties,control flow assertions,dynamic length,dynamic program optimization,high-performance execution,
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