Redundancy and parallelism tradeoffs for reliable, high-performance architectures

For decades, high performance processors have provided architectural and microarchitectural abstractions that enable applications to exploit parallelism as a means to fruitfully utilize the exponentially increasing on-chip transistor counts. With shrinking device sizes, reduced supply voltages and growing integration densities leading to logic elements becoming increasingly susceptible to transient faults, research works have established techniques to leverage existing on-chip parallelism-targeted abstractions to provide redundancy for processor pipelines, thereby increasing their resilience to transient faults. While prior works have viewed the impact of provisioning such redundancy as performance and/or implementation costs, this thesis attempts to: (1) establish the view that there exists a fundamental tradeoff between parallelism and redundancy, (2) propose efficient mechanisms that can be built to enable processor cores to operate at multiple points in this tradeoff space and argue the utility of these mechanisms, and (3) demonstrate how locality-based data flow characteristics can be exploited in novel ways to shift this tradeoff space to more efficient regions.