Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology
ISCAS（2007）
摘要
This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.
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关键词
cmos integrated circuits,voltage-controlled oscillators,multiphase realigned pll,standard cmos process,phase locked loop,2.4 mw,phase locked loops,1.8 v,multiphase direct realignment,80 to 240 mhz,voltage controlled oscillator,submicronic cmos technology,0.18 micron,cmos technology,frequency,jitter,phase noise,bandwidth
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