A low-radix and low-diameter 3D interconnection network design

Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technol- ogy. The network-on-chip (NoCs) has been proposed as a scalable and high-bandwidth fabric for interconnect design. The advent of the 3D technology has provided further op- portunity to reduce on-chip communication delay. However, the design of the 3D NoC topologies has important distinc- tions from 2D NoCs or off-chip interconnection networks. First, current 3D stacking technology allows only vertical inter-layer links. Hence, there cannot be direct connections between arbitrary nodes in different layers — the vertical connection topology are essentially fixed. Second, the 3D NoC is highly constrained by the complexity and power of routers and links. Hence, low-radix routers are preferred over high-radix routers for lower power and better heat dis- sipation. This implies long network latency due to high hop counts in network paths. In this paper, we design a low-diameter 3D network us- ing low-radix routers. Our topology leverages long wires to connect remote intra-layer nodes. We take advantage of the start-of-the-art one-hop vertical communication design and utilize lateral long wires to shorten network paths. Ef- fectively, we implement a small-to-medium sized clique net- work in different layers of a 3D chip. The resulting topology generates a diameter of 3-hop only network, using routers of the same radix as 3D mesh routers. The proposed net- work shows up to 29% of network latency reduction, up to 10% throughput improvement, and up to 24% energy reduc- tion, when compared to a 3D mesh network.