TSV-aware topology generation for 3D Clock Tree Synthesis

ISQED, pp. 300-307, 2013.

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Keywords:
3D CTSclock tree topology generationTSV-to-TSV coupling
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We study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree

Abstract:

Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solvi...More

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Introduction
  • TSV based 3D IC has attracted enough attention as a key tech­ nology to continue the scaling down trend predicted by the Moore's Law [1].
  • By considering the TEWL during the 3D clock topology generation phase, the authors can achieve up to 8.8% and 4.2% reduction of power consumption and total TSVs number respectively but with little variation of the total wirelength compared with the traditional NNG-based method.
Highlights
  • TSV based 3D IC has attracted enough attention as a key tech­ nology to continue the scaling down trend predicted by the Moore's Law [1]
  • In the previous work of 3D Clock Tree Synthesis (CTS) [8]-[10], sinks in the entire stacks are just mapped onto one layer if satisfying the total TSV number constraint
  • In order to make a uniform criterion with the traditional total wire length, we propose a TSV equivalent wire length concept (TEWL)
  • 3) Impact of considering TSVs parasitic effect in clock tree topol­ ogy generation; In order to explore the impact of TSVs parasitic on 3D clock network, we present the comparison of the results when only TSVs parasitic effects are considered in topology generation phase with the traditional NNG-based 3D clock topology generation method for different benchmarks
  • The experimental results demonstrate that our density based sorting ap­ proach can guarantee the manufacture limitations of TSVs and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs
  • Our simulation show that the number of TSVs and power consumption can be reduced by up to 89.6% and 40.16% respectively with little variation of the total wirelength compared with the traditional NNG-based method
Results
  • In this work, based on the concept of DBSCAN, the authors propose a simplified sorting algorithm to cluster the areas with high density of sink nodes, avoiding the inserted violations of adjacent TSVs as Figure 7 shows.
  • 2) The sorting results with different constraint of minimum Man­ hattan radius: One contribution of the work is to utilize a density­ aware sorting algorithm to circle area with high density of sink nodes when generating the topology of 3D clock tree.
  • Based methods if the minimum Manhattan radius r is set as Oum. The experimental results demonstrate that the proposed clustering algorithm contributes to obtain the tradeoff among power, the number of TSVs and horizontal wirelength.
  • There exits the tradeoff among power, horizontal wirelength and the number of TSVs. 3) Impact of considering TSVs parasitic effect in clock tree topol­ ogy generation; In order to explore the impact of TSVs parasitic on 3D clock network, the authors present the comparison of the results when only TSVs parasitic effects are considered in topology generation phase with the traditional NNG-based 3D clock topology generation method for different benchmarks.
  • The simulation results show that the authors can achieve up to 8.8% reduction of TSVs and about 4.2% reduction of power, and the sum of total TEWL and wirelength (ToeWL) can be reduced by 0.7% to 9.7% compared with the traditional NNG-based method.
  • TSV-to-TSV coupling effect; In order to explore the impact of the proposed 3D CTS method implementing sorting and considering TSVs parasitic effect, the authors present the comparison of the number of TSVs, the number of buffers, wirelength, power, skew with the traditional NNG-based 3D clock topology generation method for different benchmarks.
Conclusion
  • The authors propose a novel TSV-aware 3D clock tree topology generation method while taking the actual density constraint of TSVs and their parasitic and coupling effects into account.
  • The experimental results demonstrate that the density based sorting ap­ proach can guarantee the manufacture limitations of TSVs and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The authors' simulation show that the number of TSVs and power consumption can be reduced by up to 89.6% and 40.16% respectively with little variation of the total wirelength compared with the traditional NNG-based method.
Summary
  • TSV based 3D IC has attracted enough attention as a key tech­ nology to continue the scaling down trend predicted by the Moore's Law [1].
  • By considering the TEWL during the 3D clock topology generation phase, the authors can achieve up to 8.8% and 4.2% reduction of power consumption and total TSVs number respectively but with little variation of the total wirelength compared with the traditional NNG-based method.
  • In this work, based on the concept of DBSCAN, the authors propose a simplified sorting algorithm to cluster the areas with high density of sink nodes, avoiding the inserted violations of adjacent TSVs as Figure 7 shows.
  • 2) The sorting results with different constraint of minimum Man­ hattan radius: One contribution of the work is to utilize a density­ aware sorting algorithm to circle area with high density of sink nodes when generating the topology of 3D clock tree.
  • Based methods if the minimum Manhattan radius r is set as Oum. The experimental results demonstrate that the proposed clustering algorithm contributes to obtain the tradeoff among power, the number of TSVs and horizontal wirelength.
  • There exits the tradeoff among power, horizontal wirelength and the number of TSVs. 3) Impact of considering TSVs parasitic effect in clock tree topol­ ogy generation; In order to explore the impact of TSVs parasitic on 3D clock network, the authors present the comparison of the results when only TSVs parasitic effects are considered in topology generation phase with the traditional NNG-based 3D clock topology generation method for different benchmarks.
  • The simulation results show that the authors can achieve up to 8.8% reduction of TSVs and about 4.2% reduction of power, and the sum of total TEWL and wirelength (ToeWL) can be reduced by 0.7% to 9.7% compared with the traditional NNG-based method.
  • TSV-to-TSV coupling effect; In order to explore the impact of the proposed 3D CTS method implementing sorting and considering TSVs parasitic effect, the authors present the comparison of the number of TSVs, the number of buffers, wirelength, power, skew with the traditional NNG-based 3D clock topology generation method for different benchmarks.
  • The authors propose a novel TSV-aware 3D clock tree topology generation method while taking the actual density constraint of TSVs and their parasitic and coupling effects into account.
  • The experimental results demonstrate that the density based sorting ap­ proach can guarantee the manufacture limitations of TSVs and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The authors' simulation show that the number of TSVs and power consumption can be reduced by up to 89.6% and 40.16% respectively with little variation of the total wirelength compared with the traditional NNG-based method.
Tables
  • Table1: PARAMETERS DEFINITION
  • Table2: SIMULATION RESULTS WHEN CONSIDERING TSV PARASITIC AND COUPLING EFFECTS COMPARED WITH NNG-BASED 3D CTS METHODS,(N_TSV is the total number of TSVs; N_Bufs is the total number of buffers; TE WL is the TSV equivalent wire length; ToC WL is the sum of TE WL and WL)
  • Table3: OUR DETAILED SOLUTION FLOW Detailed Solution Flow Stepl: Sorting and construct the clock topology for each sorted cluster Substepl: Density aware sorting Substep2: Construct the clock topology for each sorted cluster utilizing modified DME Step2: Construct the whole 3D clock topology Substepl: Mapping unsorted sink nodes and sorted root nodes onto one layer Substep2: Paring the nearest neighbor nodes by considering TEWL Step3: Top-down buffering and embedding
  • Table4: IMPACT BY THE VARIATION OF MINIM UM MANHATTAN RADIUS r [ISPDlO_Olj, N_TSV is the total number of TSVs; N_Bufs is the total number of buffers; WL is the total horizontal wirelength r(um) O(NNG)
  • Table5: SIMULATION RESULTS OF OUR PROPOSED 3D CTS COMPARED WITH NNG BASED 3D CTS METHODS,(N_TSV is total number of TSVs; N_Bufs is the total number of buffers; TE WL is the TSV equivalent wire length; ToC WL is the sum of TE WL and WL)
  • Table6: SINK NODES SORTED RESULTS FOR DIFFERENT BENCHMARKS
Download tables as Excel
Related work
  • In the last few years, several researchers have conducted fruitful researches on 3D clock design, which mainly focus on zero (bounded) skew aware 3D clock network design [5], slew aware 3D clock network design [8], low power 3D clock network design [9], robust aware 3D clock network design [6], [7] and testable aware 3D clock network design [4], [14]. Zhao et al [14] and Kim et al [4]focused on clock tree synthesis with pre-bond testability for 3D stacked IC design.

    For 3D abstract tree topology generation, there are three existing algorithms 3D-MMM [6], [8], [9], MMM-3D [3] and NNG-based algorithm(Nearest Neighbor Graph) [10]. Both of 3D-MMM and MMM-3D are based on 2D MMM(method of means and medians) algorithm proposed in [15]. They partition a subset of sinks vertically and horizontally according to the given TSV number threshold but not the TSVs density. Besides, NNG-based 3D clock topology generation method is based on the slightly modification of the traditional NNG method [16].
Funding
  • In addition, the coupling effect between two adjacent TSVs in 3D ICs could be very problematic because of the big size of TSVs, which could lead to the increase of path delay and power consumption, and lThis work was supported by IBM, National Science and Technology Major Project (20IOZXOI030-001-001-04, 2011ZXOI035-001-001-002) and National Natural Science Foundation of China (No 61028006,61261160501), and Tsinghua University Initiative Scientific Research Program
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