Parallel Implementation Of Cholesky Llt-Algorithm In Fpga-Based Processor

The fixed-size processor array architecture, which is intended for realization of matrix LLT-decomposition based on Cholesky algorithm, is proposed. In order to implement this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. The AU is intended for configuring in the Xilinx Virtex4 FPGAs, and its hardware complexity is much less than the complexity of similar AUs operating with floating-point numbers.