Ultra-Low Power 2.4 Ghz Cmos Receiver Front-End For Sensor Nodes

This paper presents a fully integrated receiver front-end for a 2.4GHz RF transceiver. A system level design for the radio front end for which these components are designed is also presented. The proposed receiver front end (Low-Noise Amplifier, Single-to-Differential Converter and Mixer) is based on a direct conversion architecture designed in 0.18 mu m CMOS technology. It takes advantage of on-chip single to differential signal conversion to avoid the use of cost intensive off-chip balun and external passives. The post layout simulations of front end show that the RF front-end achieves a voltage gain of 8dB without the baseband amplifier, a noise figure of 8.9 dB and IIP3 better than -15 dBm. The flicker noise corner is less than 10 KHz, with a nominal DC offset. It consumes less than 1.6 mA from a 1.8V supply.