Highly Parallel FPGA Emulation for LDPC Error Floor Characterization in Perpendicular Magnetic Recording Channel
IEEE Transactions on Magnetics（2009）
摘要
Low-density parity-check (LDPC) codes offer a promising error correction approach for high-density magnetic recording systems due to their near-Shannon limit error-correcting performance. However, evaluation of LDPC codes at the extremely low bit error rates (BER) required by hard disk drive systems, typically around 10-12 to 10- 15, cannot be carried out on high-performance workstations using con...
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关键词
Field programmable gate arrays,Emulation,Parity check codes,Perpendicular magnetic recording,Bit error rate,Error correction codes,Magnetic recording,Hard disks,Workstations,Monte Carlo methods
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