Statistical performance analysis and optimization of digital circuits

Aggressive device scaling has made it imperative to account for process variations in the design flow. A robust model of process variations is an essential requirement for any meaningful variation aware design analysis and optimization. In the first part of this work, we present an approach to extract spatial variation models based on the theory of spatial statistics. The proposed approach uses the concept of variogram function that represents how parameters can co-vary as a function of spatial distance. In the second part of this work, we present a new approach to compute the statistical maximum for improving the accuracy of existing statistical timing analysis approaches. Existing approaches use the results given by Clark for analytically computing the mean and variance of the maximum of two normal arrival time distributions. In practice due to the nonlinear maximum operation the arrival time distributions are found to be non-normal and skewed. Using skew-normal representation for arrival time distribution, analytical results are derived for propagating the skewed arrival time distributions. We then present an optimization method for yield optimization under simultaneous leakage power and timing constraints. The optimization approach uses a leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power and performance to enable accurate computation of circuit yield under power and delay limits. The key to our approach is a new method to incrementally compute the gradient of yield with respect to gate sizes in the circuit with high efficiency and accuracy. Finally, we present a framework to perform full-chip gate oxide reliability analysis in the presence of process variations. The conventional approach for full chip oxide reliability analysis scales pre-characterized device level oxide reliability models assuming a uniform oxide thickness for all devices. Due to manufacturing variations, an alternative reliability analysis approach is needed for modeling oxide thickness variations. A statistical approach is proposed for performing chip level gate oxide reliability analysis while considering both die-to-die and within-die components of thickness variation.