1.2v 300mhz Cmos Pll For Clock Generation In 0.35um Process

In this paper, a 1.2V 0.35um CMOS PLL with a wide frequency range for clock generation systems is presented. A new full swing PFD has been designed to extend the operating frequency range. The charge pump is a drain switching circuit with high compliance regulated input cascode current mirrors. A voltage booster is used to supply the charge pump and extend its output voltage range. The oscillator is a full swing pseudo-differential CMOS ring structure. The typical oscillator tuning range is 30 to 300MHz. Cycle-to-cycle jitter due to a 100mV VDD variation (pk-pk) was 45ps. The current consumption of the PLL is 537uA at 300MHz.