A timing-driven block placer based on sequence pair model

ASP-DAC(1999)

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摘要
In this paper, an effective timing-driven building block placer is proposed. Interconnection delay is modeled and included during the placing process in order to minimize the area and wirelength, as well as to satisfy the timing constraints in the algorithm. The simulated annealing technique for constrained optimization problem and the sequence pair model proposed by H. Murata et al. (1996) are applied. Not only the timing constraint but also the aspect ratio is taken into account in the search process. The experimental results demonstrate the algorithm can improve the timing delay and obtain good placement
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关键词
sequence pair model,interconnection delay,logic cad,timing-driven block placer,building block placer,timing-driven,floorplanning,np-hard problem,simulated annealing algorithm.,circuit optimisation,sequence pair,timing,circuit layout cad,algorithm timing constraints,search process,vlsi,timing delay,goal function,constrained optimization problem,integrated circuit layout,simulated annealing,building block placement,aspect ratio,np hard problem,capacitance,stochastic processes,simulated annealing algorithm,satisfiability
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