Potential of and Issues with Multiple-Stressor Technology in High-Performance 45 nm Generation Devices

In this paper, we describe multiple-stressor technology (MST) for high-performance 45-nm-node devices. The combination of two or more stressors, namely, polygate stressor (PGS)/tensile stress liner (SL) for n-channel field-effect transistor (NFET), and embedded SiGe/compressive SL for p-channel field-effect transistor (PFET), is integrated into complementary metaloxide-semiconductor (CMOS) process and its potential for device performance enhancement is investigated. Moreover, the issues of MST are also discussed from the viewpoint of variations in device characteristics under an extremely high channel strain, which are not pronounced in the previous technology with its relatively low strains.