A Routing Fabric For Monolithically Stacked 3d-Fpga

A previous study on the benefits of monolithically stacked 3D-FPGA has estimated a 3.2x improvement in logic density, a 1.7x improvement in delay, and a 1.7x improvement, in dynamic power consumption over it baseline 2D-FPGA with no change in architecture. This paper describes a, new routing fabric and shows that, a 3D-FPGA using this fabric call achieve a 3.3x improvement in logic density, a 2.35x improvement in delay, and a 2.82x improvement in dynamic power consumption over the same baseline 2D-FPGA. The additional improvements in delay and power consumption axe achieved by reducing net loading in several i) Only Single and Double interconnect segments are ways: used. This reduces the total interconnect length used to implement each net. (ii) The routing Fabric is hierarchical. Each logic block's inputs and outputs connect first to local segments segments. These segments can be then programmably connected to local segments in neighboring routing blocks via programmable buffers and/or to interconnect segments in routing channels via muxes with buffered outputs. (iii) Interconnect segments can be directly connected to form longer segments using programmable buffers without going through routing blocks. (iv) The routing block provides switching capability beyond that of a, conventional switch box. A 3D-FPGA using this new routing fabric call be realized by Stacking two configuration memory layers and a Switch layer on top of a, standard CMOS layer with a total of 12 metal layers interspersed between them. A CAD flow based on VPR, with appropriate modifications to the routing graph generation and routing algorithm is developed and used in the performance analysis.