A circuit level fault model for resistive shorts of MOS gate oxide

MTV, pp. 97-102, 2004.

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Abstract:

Previous researchers in logic testing focused on shorts in MOS gate oxides that have zero-resistance. However, most shorts are resistive and may cause delay faults. In this paper, we propose a simple and realistic delay fault model for gate oxide shorts. A reasonably accurate method is proposed to compute delay change due to resistive sho...More

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