K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits

ITC, pp. 223-231, 2004.

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Abstract:

To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are inefficient in automatically identifying the longest testable paths due to the high computational complexity. In this work a test generation methodology for scan-based synchronous sequential ...More

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