The Effect of FPGA Size on Software Speedup from Hardware / Software Partitioning

We examine the relationship between FPGA size and software speedup when an on-chip FPGA is used to implement critical software loops through hardware/software partitioning. We studied seven benchmark programs taken from Mediabench and Netbench. We profiled the programs on the SimpleScalar architecture, rewrote the critical loops in VHDL, synthesized and mapped those loops to a Xilinx FPGA, and calculated the gate requirements and performance speedups. We created several versions of each program, each version having successively more critical code moved to the FPGA, to see the relationship between size and speedup. Our results show that surprisingly few FPGA gates are needed to obtain most of the reasonably achievable speedup – an average speedup of 6x was obtained with only about 20,000 gates.