Fabrication cost analysis for 2D, 2.5D, and 3D IC designs

The interposer-based 2.5D technology has some advantages that are provided in the 3D technology, such as low interconnect delay, and high bandwidth, etc. In addition, the 2.5D technology can mitigate area overhead of TSVs and help reduce the temperature and binding cost. An extra interposer layer, however, is introduced for interconnect in a 2.5D design. With 2D, 2.5D, and 3D design options, the fabrication cost is an important metric to decide which technology should be adopted for different designs. In this paper, we present a cost estimation method for 2.5D ICs by extending a 3D floorplanning tool and the 3D cost models. This method can provide an estimated cost comparison among three technologies as a reference of choosing the strategy during the early design stage. We apply our method to several design benchmarks and compare the cost with different design strategies. Moreover, the interconnect delay and temperature results are also provided for comparison.