A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power.

This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators w...