Fast interconnect synthesis with layer assignment
ISPD, pp. 71-77, 2008.
As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, ...More
Get fulltext within 24h
Full Text (Upload PDF)
PPT (Upload PPT)