Fast interconnect synthesis with layer assignment

ISPD, pp. 71-77, 2008.

Cited by: 44|Bibtex|Views4|Links
EI
Keywords:
design flowconcurrent buffer insertionbuffer insertionwire sizingdesign sizeMore(6+)

Abstract:

As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, ...More

Code:

Data:

Your rating :
0

 

Tags
Comments