Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1294-1307, 2014.

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Keywords:
MOSFETsemiconductor device modelsSRAM chipstechnology CAD (electronics)

Abstract:

Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using t...More

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