A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities

The two most commonly used hash algorithms are MD5 and SHA-I. Both of them. have a similar structure and they share many common resources. Several FPGA-based implementations of both algorithms have been published. However, methods to combine the two algorithms into a single compact, but fast, design have not been extensively studied. This paper presents a compact architecture for combining these commonly used algorithms into a single design by utilizing both the common structure and the similarities in the operations they use. The method results in a very compact implementation. The design was implemented on a Xilinx Virtex-II XC2V2000-6 FPGA device and it required only 1882 slices and operated at a clock frequency of 77.6 MHz, achieving throughputs of 602 Mbps and 485 Mbps for MD5 and SHA-I, respectively.