Domain-Specific Reconfigurable PAL/PLA Creation for SoC

As we move to System-on-a-Chip (SoC), where multiple types of resources are integrated on a single chip, it is important to consider how to best integrate reconfigurability into these systems. Reprogrammable logic can add general computing ability, provide run-time reconfigurability, or even be used for post-fabrication modifications. Also, by catering the logic to the SoC domain, additional area/delay/power gains can be achieved over current, more general reconfigurable fabrics. This paper presents tools that automate the creation of domain specific PLAs and PALs for SoC, including an Architecture Generator for making optimized arrays and a Layout Generator for creating efficient layouts. By intelligently mapping netlists to PLA and PAL arrays, we can reduce 63%-75% of the programmable connections in the array, creating delay gains of 17%-32% over unoptimized arrays.