Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA, pp. 37-46, 1999.
cluster-based logic blocktiming-driven packingfpga speedram
In this papel; we investigate the speed and area-eficiency of FPGAs employing "logic clusters" containing multiple LUTs and registers as their logic block. We introduce a new, timing-driven tool (T-VPack) to "pack" LUTs and registers into these logic clusters, and we show that this algorithm is superior to an existing packing algorithm. T...More
Best Paper of FPGA, 1999