Compositional interaction specifications for SystemC

MEMOCODE(2006)

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摘要
SystemC is being widely used for system-level modeling of system-on-chip. When designing this class of system, one of the main challenges is to guarantee the correctness of the implementation. This can be especially difficult for designs that are composed of concurrent components with lot of interactions. Most designers use a component-based design approach, where one has an informal idea of how the design should behave, define component specifications, implement and assemble the components into a program, and then check for correctness by simulating the design with a number of testbenches. With this methodology, bugs often go undetected because when using simulation, it is very difficult to test for all possible interactions. To overcome this limitation, our goal is to establish a specification and verification methodology for SystemC. To address the scalability issue, which is a serious limiting factor in state-based verification approaches, we use the concepts of behavioral types; allowing us to effectively infer system properties from properties of its components. In this paper, we answer the following questions: (1) what is a behavioral type? (2) how are behavioral type defined? and (3) how to use the behavioral types in a compositional verification methodology.
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关键词
systemc verification,behavioral types,state-based verification,compositional interaction specification,systemc specification,scalability,system testing,formal specifications,component based design,formal specification,system on chip,design methodology,formal verification,context modeling,hardware description languages,system on a chip,computer bugs,assembly,limiting factor
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