A 1-V 15-Bit Audio ΔΣ-ADC in 0.18 µm CMOS.
IEEE Trans. on Circuits and Systems(2012)
摘要
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed- forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub- filters. Timing multiplexing and resource reuse methodology are employed for low hardware cost. The ADC is programmed to adapt 4K 8K 16K applications. Over 90dB SNDR performance can be achieved under various bandwidths while the total power dissipation is 360μW. The modulator occupies 0.3mm2 and decimation filter occupies 0.2mm2.
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关键词
power 360 muw,cmos analogue integrated circuits,analogue-digital conversion,power dissipation,sndr,amplifiers,resource reuse methodology,timing multiplexing,feed-forward path,delta-sigma modulation,voltage 1 v,audio application,single stage amplifier,δς adc,cascade subfilter,second order modulator,audio signal processing,word length 15 bit,decimation filter,cmos,nonlinear gain effect,high power efficiency,size 0.18 micron,delta sigma modulation,capacitors,cmos integrated circuits,bandwidth,quantization,multiplexing,modulation,noise
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