A 4.5 Mw/gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core with Optional Cleanup PLL in 65 Nm CMOS.
IEEE Journal of Solid-State Circuits（2010）
Key words
High-speed serial links,clock generation,clock and data recovery,CDR,source-synchronous link,jitter,polyphase filter,phase-locked loop,PLL,BIST,cross-talk,X-talk,forwarded clock
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