A systematic DFT procedure for library cells
VTS（1999）
摘要
We present an automated procedure for improving the testability of a product by improving the testability of cells in the cell library. This method was applied to a scan flip-flop from Cyrix's standard cell library. Based on this analysis, some design and layout changes were suggested, which brought down the probability of difficult-to-detect faults by 70%, without compromising the performance or increasing the area of the circuit
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关键词
systematic dft procedure,layout change,automated procedure,sequential circuits,logic cad,standard cell library,scan flip-flop,circuit area,cell library,cyrix,library cells,circuit layout cad,layout changes,cellular arrays,difficult-to-detect faults,flip-flops,design for testability,software libraries,difficult-to-detect fault,fault detection,fabrication,data mining,sequential analysis
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