A Novel Multifin Dynamic Random Access Memory Periphery Transistor Technology Using a Spacer Patterning through Gate Polycrystalline Silicon Technique

A new technique that integrates the metal gate multifin field effect transistor (multi-FinFET) and the conventional polycrystalline silicon (poly-Si) gate planar FET is proposed. It solves the problems of the previous scheme, such as the complicated process integration due to the coexistence of TiN gate FinFETs and poly-Si gate planar FETs, the fin width consumption by multiple gate oxidation, the large fin pitch limited by the resolution of lithography, and the gap-filling ability of shallow trench isolation (STI). The newly proposed technique forms multifin structures by spacer patterning through the gate poly-Si electrode for planar FETs. The drain current gain due to an increase in effective channel width is estimated, and the basic electrical characteristics of a multi-FinFET are evaluated. (C) 2009 The Japan Society of Applied Physics