Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

    FPGA, pp. 69-78, 1999.

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    reconfigurable computing arraylut utilizationfloorplanningplacementtabu searchMore(3+)

    Abstract:

    FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficientsilicon usage. Rather, since interco...More

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    Best Paper of FPGA, 1999
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