A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple constraints set by industry standards ask for a receiver architecture capable of simultaneously addressing channel loss impairments, high frequency-difference tracking and low serial to parallel latency. An adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized s...