Supporting high-performance pipelined computation in commodity-style fpgas
Supporting high-performance pipelined computation in commodity-style fpgas(2008)
摘要
Although the popularity of Field Programmable Gate Arrays, or FPGAs, is a testament to their unique mixture of flexibility and ease of use, this adaptability can come at price. The programmable nature of FPGAs introduces significant inefficiencies that can limit the maximum clock frequency of mapped circuits. While there are multiple techniques developers apply to mitigate this performance penalty, these enhancements can generate an enormous number of additional registers. These heavily registered circuits have fundamentally different characteristics and create significant problems for many different aspects of FPGA application development. This dissertation investigates the concerns that arise for both FPGA physical design tools and the architectures themselves. FPGA Development Tools. High quality compilation tools are necessary to create fast and efficient FPGA-based applications. However, heavily registered circuits can confuse existing packing, placement, retiming, and routing tools. This dissertation examines the roots of these problems and suggests new timing-driven and register-aware physical design techniques. These new approaches are shown to significantly improve achievable results, potentially doubling the speed of mapped circuits. FPGA Architectures. Heavily registered applications can also overwhelm the register resources provided by classical FPGA architectures. While there have been previous research efforts to build FPGAs with better register support, most have suggested very specialized systems that depart significantly from conventional architectures and toolflows. This dissertation explores a different approach and investigates the practical advantages of making minimally invasive architectural changes to both FPGA logic blocks and interconnect resources. These architectural choices can affect the required area of implemented designs by a factor two. This dissertation shows that netlists with a large number of registers can significantly change the problems presented to CAD tools and the demands placed on FPGA architectures. Failing to acknowledge these changes can be costly. That said, some problems are likely more pressing than others. Furthermore, although this dissertation identifies many of the aspects of an FPGA architecture that can dramatically affect the required area of deeply pipelined or C-slowed applications, this work merely scratches the surface and much more research is necessary to determine what future FPGAs should look like.
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关键词
mapped circuit,commodity-style fpgas,FPGA physical design tool,dissertation shows,FPGA architecture,high-performance pipelined computation,FPGA application development,FPGA Development Tools,required area,classical FPGA architecture,FPGA logic block,FPGA Architectures
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