Next generation of Deep Trench Isolation for Smart Power technologies with 120V high-voltage devices

A new Deep Trench Isolation (DTI) structure with high-voltage capability (BV > 150 V) and latch-up suppression (log(I(c)/I(e)) < - 2 in adjacent pockets) is experimentally demonstrated in this work. The new DTI is implemented in a Nepi/BLN/N(-)/P(+) Silicon stack by using a 0.18 mu m CMOS-based platform. Moreover the advantages and design limitations of the new DTI are investigated by TCAD simulations and analytical models, being compared to its DTI predecessor in a Nepi/BLN/P(-)/P(+) stack. (C) 2010 Elsevier Ltd. All rights reserved.