A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration
ESSCIRC（2012）
摘要
We report an 11-b 20-Ms/s pipelined ADC in 0.18-μm CMOS with a novel dual-mode-based digital background calibration method that altogether corrects errors caused by gain insufficiency, gain nonlinearity, and capacitor mismatches. The calibration enables an intentional use of low-gain single-stage op amps instead of conventional high-gain multi-stage op amps, with which we achieve a total ADC power dissipation of 2.9 mW and a short convergence time of 105. The calibration improves the SNDR from 45 dB to 60 dB, and the SFDR from 50 dB to 86 dB. The figure-of-merit is 174 fJ/conversion-step.
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关键词
high-gain multistage op amps,cmos integrated circuits,calibration,analogue-digital conversion,pipelined adc,adc power dissipation,word length 11 bit,capacitor mismatches,operational amplifiers,short convergence time,low-power electronics,capacitors,convergence,size 0.18 mum,cmos integrated circuit,power 2.9 mw,gain insufficiency,gain nonlinearity,dual-mode-based digital background calibration,low-gain single-stage op amps,gain,charge transfer,low power electronics
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