A design environment for high throughput, low power dedicated signal processing systems
IEEE Journal of Solid-State Circuits(2001)
摘要
A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined Simulink and floorplan description drives automatic layout generation. Automatic characterization of layout improves system-level estimates. The flow is demonstrated on the subsystems of CDMA and OFDM receivers and a 300 k transistor test-chip
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关键词
OFDM modulation,application specific integrated circuits,circuit layout CAD,code division multiple access,digital signal processing chips,digital simulation,integrated circuit layout,CDMA,OFDM,Simulink,automatic layout generation,dedicated signal processing systems,floorplan description,hierarchical automated design flow,modular framework,system-level estimates,transistor test-chip,
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