Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency
msra(2007)
摘要
Coarse-grained reconfigurable architectures (CGRAs) have the potential to offer performance approaching an ASIC with the flexibility, within an application domain, similar to a digital signal processor. In the past, coarse- grained reconfigurable architectures have been encum- bered by challenging programming models that are ei- ther too far removed from the hardware to offer reason- able performance or bury the programmer in the minu- tiae of hardware specification. Additionally, the ratio of performance to power hasn't been compelling enough to overcome the hurdles of the programming model to drive adoption. The goal of our research is to improve the power efficiency of a CGRA at an architectural level, with re- spect to a traditional island-style FPGA. Additionally, we are continuing previous research into a unified map- ping tool that simplifies the scheduling, placement, and routing of an application onto a CGRA.
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