Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch

Robert Gibbins

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R. Dean Adams

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Thomas Eckenrode

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Michael Ouellette

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Yuejian Wu

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MTDT, pp. 83-83, 2002.

Cited by: 3|Views8

Keywords:

STS-1 Switchdata memory bit countconventional memorycustom programmable BIST solutionspecific 9-port SRAMMore(6+)

Abstract:

This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST...More

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