Timing Analysis in Presence of Power Supply and Ground Voltage Variations

Given the sensitivity of circuit delay to supply and ground voltagevalues, static timing analysis (STA) must take into account supplyvoltage variations. Existing STA techniques allow one to verifythe timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independentnor totally dependent. In this work, we consider the supply andground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supplyvoltage values are not known exactly, but that only upper/lowerbounds on them are known. In this framework, we propose newtiming models for logic gates and identify the worst-case voltagecon gurations for individual gates and for simple paths. We thengive an STA technique that provides the worst-case circuit delaytaking supply variations into account.