An Optimal Performance-Driven Technology Mapping Algorithm For Lut-Based Fpgas Under Arbitrary Net-Delay Models

The field programmable gate-array (FPGA) has become animportant technology in VLSI ASIC designs. Most existingperformance-driven technology mapping algorithms forLookup-table (LUT) based FPGA designs are based on unitdelay model. In this paper we present an efficient algorithmwhich finds an optimal technology mapping solution withminimum delay under arbitrary net delay models for LUTbasedFPGA designs. The key step of this algorithm is thecomputation of a minimum height K-feasible cut in ...