Bump Wafer Level Packaging A New Packaging Platform (Not Only) For Memory Products

A new wafer level packaging technology will be presented; properties and potential will be discussed. Heart of the technology is the realisation of a resilient bump contact system, which allows a double functionality for test and for application:A: it serves as a flexible contact system for in-house tests using a simple,flat conductor board instead of a conventional complex (needle) probecardB: the resilient interconnect bump system allows a high increase in board level reliability.Not using solder in the WLP process, realising an Au/Au contact in test and burn-in with an (on chip)flexible contact system gives very stable electrical test connection up to very high frequencies. Bundling the benefit of the low cost WLP technology with the large reduction potential in test complexity (full wafer contact for test and burn-in), this technology has special benefit for memory products. Conventional WLP technologies use rigid solder bump interconnect elements. These technologies are restricted in reliability for large chips (w/o underfill) and they have a test unfriendly contact system (solder balls). Both disadvantages are overcome by using a flexible interconnect system developed by Infineon Technologies.